RFIC/Analog Design Engineer – PLL
Responsible for high-performance and low power design of RF Frequency Synthesizers and PLLs for LTE, GNSS, WiFi, Bluetooth, Zigbee and other communication systems.
- MS or PhD in Electrical Engineering with 7+ years of experience in RF/Analog IC design with advanced CMOS technology nodes. SOI technology experience a plus.
- Detailed understanding of RF Frequency Synthesizer and PLL circuit design. Direct tape-out experience with one or more of the following: Charge-Pump based PLLs, Fractional-N PLLs, Digital PLLs, LC-VCO (> 6GHz), Ring Oscillator VCO, XTAL Oscillators, Frequency Dividers and LO Generation circuits.
- Good understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, offset and other analog impairments.
- Good understanding of CMOS device physics, RF device modeling, device noise parameters, inductor modeling and EM simulation.
- Knowledge of QFN & CSP packaging effects, supply isolations, circuit layout for optimum RF performance, EM effects, PEX (post-layout parasitic extraction).
- Experience in using development tools including Cadence Virtuoso, Spectre RF, EMX & MATLAB.
- Understanding of system specifications and ability to translate system requirement into circuit requirement at IC level.
- Hands-on experience in silicon characterization and debug.
- Team player with good verbal and written communication skills along with excellent presentations skills (MS Office Suite). Strong sense of urgency.
- 12+ years of RF/Analog IC design.
- Experience as RF Frequency Synthesizer and PLL Technical Lead.
Remote (hybrid) option for the right candidate(s).